Complementary metal oxide semiconductor (CMOS) microprocessors typically comprise one or more integrated circuit (IC) chips. Each IC chip includes thousands and perhaps millions of field effect transistors (NFETS and PFETS) which are used to construct memory arrays, latches, and other combinatorial logic elements. These circuits must reliably store or process data during every microprocessor cycle (t.sub.cycle) over the lifetime (.delta.) of the microprocessor.
The term hot-electron (HE) effect refers to the phenomenon of electrons which originate from FET surface channel currents, from impact ionization currents at the FET drain junction, or from substrate leakage currents. Channel hot electrons originate from channel conduction current near the drain junction. Electrons drifting from the drain may gain sufficient energy to enter into the gate, or they may collide with the silicon atoms and generate electron-hole pairs. The hole adds to substrate current, and the secondary electron may be injected into the gate of a subsequent FET (see e.g., M. Annaratone, H.B. Digital CMOS Circuit Design, Kluwer Academic Publishers, Norwell Mass., p. 39, (1986)). As these secondary electrons accumulate in the gate, the FET threshold voltage V.sub.T shifts and the internal resistance of the device changes. Device current I.sub.d is proportional to both the internal resistance of the device and (V.sub.GS -V.sub.T).sup.2. Therefore, as the threshold voltage V.sub.T the internal resistance changes, the current drive capability I.sub.d of the device changes. This time dependent, drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d must be less than 0.1 according to conventional hot-electron reliability criteria.
Drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d is a wear-out effect which reduces circuit reliability, because it also causes circuit propagation delay degradation .DELTA.t.sub.pd (.tau.), which may result in intermittent timing-faults over microprocessor circuit lifetime (.delta.). Variances in the circuit propagation delay, .DELTA.t.sub.pd (.tau.)/t.sub.pd are proportional to the time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d. Time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d and circuit propagation delay degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd are both dependent on manufacturing process variations, circuit design, and microprocessor application factors of temperature, voltage and lifetime. The reduction in microprocessor reliability over circuit lifetime is especially applicable to microprocessors having short transistor channel lengths that are sensitive to hot-electron effects, because drain current degradation is proportional to the effective channel length of a transistor.
Accordingly, when assessing microprocessor reliability, circuit designers must attempt to determine time dependent drain current degradation .DELTA.I.sub.d (.tau.)/I.sub.d. Because this term is proportional to variances in circuit propagation delay .DELTA.t.sub.pd (.tau.)/t.sub.pd, the circuit designer may assess the drain current degradation by analyzing .DELTA.t.sub.pd (.tau.)/t.sub.pd. Circuit propagation delay degradation which is caused by hot-electron effects may then be used to determine if a particular circuit satisfies established timing criteria. In doing so, designers insure proper timing of data and control signals propagating through the circuit, by insuring that the microprocessor tolerate circuit propagation delay degradation .DELTA.t.sub.pd (.tau.)/t.sub.pd caused by hot-electron effects.
The hot-electron effects on propagation degradation are considered during circuit level design for each transistor in the circuit (see, e.g. T. J. O'Gorman, ADCHECK Circuit Reliability Program, IBM.RTM. Microelectronics Division, May, 1994). Typically, microprocessors which are particularly sensitive to hot-electron effects are identified by testing a batch of microprocessors at a power supply voltage that is lower than the normal application voltage. The test is based on the principle that the lower test voltage has an adverse effect on microprocessor timing which is similar to that experienced by the microprocessor, due to propagation delay degradation, under normal application voltage at circuit end-of-life. Microprocessors so identified may then be discarded to improve the overall reliability of a particular distribution of microprocessors.
The difference between the normal application power supply voltage and the lower test voltage is referred to as the "guard-band", the magnitude of which must be properly determined in order to optimize the results of the microprocessor end-of-life timing degradation simulation. If the guard-band (voltage differential) is set too high, the test voltage will be lowered too much, reducing product yield. On the other hand, if the guard-band is set too low, the test voltage will not be lowered enough, reducing product reliability. Typically, the guard-band will be set too high or too low because it is not specifically tailored to the application specific logic and physical circuit design of the microprocessor.
It is therefore an object of the present invention to provide a self-calibrating method that quantifies the test voltage for a microprocessor's application specific technology, design, and environment, to accommodate for propagation delay degradation caused by hot-electron effects.